1. Field of the Invention
The present invention relates generally to semiconductor device packages that employ multiple semiconductor dice. More specifically, the present invention relates to methods and apparatus for increasing integrated circuit density by employing a plurality of semiconductor dice in semiconductor packages while utilizing a single lead frame.
2. State of the Art
High performance, low cost, increased miniaturization of components, and greater packaging density of integrated circuits have long been the goals of the computer industry. Greater integrated circuit density, for a given level of active component and internal conductor density, is conventionally limited by the space available within a packaging envelope and by the surface area, or xe2x80x9creal estate,xe2x80x9d available on a carrier substrate such as a printed circuit board. In addition, simplicity and reduced processing of semiconductor die assemblies are preferable. For instance, reduction of parts and processing steps reduces the cost of semiconductor components.
For conventional lead frame-mounted semiconductor dice, space limitations are a result of the basic design. Conventional lead frame design inherently limits potential single-die package density because the die-attach paddle of the lead frame is conventionally as large as or larger than the die residing on the paddle. The larger the die, the less space (relative to size of the die) that remains around the periphery of the die-attach paddle for forming the requisite electrical connections such as with wire bonds and for encapsulation by packaging material.
One known method of increasing integrated circuit density is set forth in U.S. Pat. No. 5,012,323 to Farnworth. Farnworth teaches the combining of a pair of dice mounted on opposing sides of a lead frame. An upper die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. The lower die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative, film layer. The bond pads on both the upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum bond wires. The lower die is slightly larger than the upper die so that the lower die bond pads are accessible from above through an aperture in the lead frame such that wire bonds can be made from these bond pads to lead extensions. However, this arrangement has a major disadvantage from a production standpoint, since differently sized dice are required. Furthermore, such a design may allow for a build-up of thermal energy between the two dice and does not provide an effective means of dissipating such thermal energy. Additionally, the use of differently sized dice tends to yield a mechanically and thermally unbalanced package. For example, the two differently sized dice may generate and dissipate heat at different rates and may also expand and contract at different rates, resulting in undesirable stress/strain patterns within the package.
U.S. Pat. No. 5,291,061 to Ball teaches a multiple stacked die device that contains up to four dice and which does not exceed the height of then-current single die packages. The low profile of the device is achieved by close-tolerance stacking, which is made possible by a low-loop-profile wire bonding operation and thin-adhesive layers between the dice of the stack. However, although Ball secures all of the dice to a single lead frame, the wire bonds tend to become excessively long and/or the lead frame must be modified to accommodate the wire bonding of the upper semiconductor dice. Further, such an arrangement may again yield a thermally unbalanced package, particularly with only one die of the plurality of dice being disposed on the die paddle of the lead frame.
U.S. Pat. No. 5,804,874 to An et al. discloses the stacking of two or more identical leads-over-chip (xe2x80x9cLOCxe2x80x9d) configured semiconductor dice facing in the same direction. A lower die is adhered by its active surface to leads of a lower lead frame and wire bonded in LOC fashion, after which the active surface of at least one other die is adhered to leads of an upper lead frame in LOC fashion, then adhesively back bonded to the upper surface of the lower lead frame. The leads of the upper lead frame are electrically connected to those of the lower lead frame by thermocompression bonding. The An device, while providing increased circuit density, requires at least two differently configured LOC lead frames and that bond pads of both dice be wire bonded to their corresponding leads before the at least two dice are secured together. Moreover, the asymmetrical die arrangement and coverage of the wire bonds of the lower die by the upper die may induce an irregular flow front of filled polymer encapsulant material as the assembly is encapsulated by transfer molding, resulting in incomplete encapsulation without voids and increased probability of bond wire sweep and consequent shorting.
U.S. Pat. No. 6,252,299 to Masuda et al. discloses an LOC-type semiconductor package wherein an upper die and a lower die, each with centrally located bond pads, are electrically connected to separate lead fingers of respective lead frames. In addition, the upper and lower dice are configured such that the circuit-bearing or active surfaces of each die are opposed to each other. Thus, the Masuda invention employs multiple lead frames, adding to the material and processing costs and complexities of the packaged device. Further, the upper and lower dice are arranged in a back-to-back configuration and present issues of thermal energy build-up similar to those discussed above.
U.S. Pat. No. 6,087,718, issued to Cho, discloses a stacked-type semiconductor package wherein an upper die with peripherally located bond pads and a lower die with centrally located bond pads are electrically connected to a single lead frame. However, the use of differently configured semiconductor dice in Cho may be somewhat undesirable as it requires a specially configured lead frame which is amenable to the attachment and operative connection of two differently configured semiconductor dice. Further, as discussed above, differing rates of heat generation, heat dissipation, expansion and contraction may result from the use of two differently sized and configured dice.
U.S. patent application Ser. No. 10/093,332, entitled METHODS AND APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, applied for by Bolken and assigned to the Assignee of the present invention, discloses the stacking of two similarly configured semiconductor dice facing in the same direction. A lower die is adhered by its active surface to the leads of a lead frame and wire bonded in an LOC fashion. The second die is adhesively back bonded to the upper surface of the lead frame and is electrically connected to the lead frame by means of wire bonds which extend from the centrally located bond pads of the second die outwardly beyond the periphery thereof. The Bolken device, while providing increased circuit density, requires wire bonds of excessive length and may require specially configured wire bonds to maintain proper structural rigidity throughout the length of the wires used in forming such bonds.
Thus, it would be advantageous to develop a technique and device for increasing integrated circuit density in a semiconductor device package utilizing multiple semiconductor dice that are electrically bonded to a single lead frame.
In would further be advantageous if such a package could be assembled and fabricated using conventional components and conventional processes such that the package may be produced in current facilities without substantial disruption of current work flow processes.
It would also be advantageous if such a semiconductor package device allowed for increased dissipation of heat or thermal energy that tends to build up in multiple-die packages. For example, it would be advantageous to provide a thermally and mechanically balanced package.
In accordance with one aspect of the invention, a semiconductor device package is provided. The package includes a lead frame including a die paddle and a plurality of lead fingers and a first semiconductor die having an active surface and a plurality of bond pads disposed on the active surface. The active surface of the first semiconductor die is adhered to an underside of the die paddle and at least one of the plurality of bond pads is electrically connected to at least one of the plurality of lead fingers.
The semiconductor device package may further comprise a second semiconductor die having an active surface, a surface opposing the active surface and a plurality of bond pads disposed on the active surface. The opposing surface of the second semiconductor die may be adhered to the upper side of the die paddle with at least one of the plurality of bond pads being electrically coupled with at least one of the lead fingers.
The first semiconductor die and second semiconductor die may be substantially identical to one another and have corresponding bond pads commonly electrically coupled with specified lead fingers.
A thermally conductive material may be used to adhere one or more of the semiconductor dice with the die paddle to increase heat transfer to the die paddle and through any tie bars coupled therewith.
In accordance with another aspect of the present invention, another semiconductor device package is provided. The semiconductor device package includes a lead frame having a centrally located die paddle and a plurality of lead fingers arranged about a periphery of the die paddle. A first semiconductor die having an active surface and a plurality of bond pads disposed on the active surface is adhered to the underside of the die paddle along its active surface. A second semiconductor die having an active surface, a second opposing surface and a plurality of bond pads disposed on the active surface thereof is adhered to the upper side of the die paddle along its second opposing surface. A first electrical connection is formed between a first bond pad of the plurality of bond pads of the first semiconductor die and a first lead finger of the plurality of lead fingers. A second electrical connection is formed between a first bond pad of the plurality of bond pads of the second semiconductor die and a second lead finger of the plurality of lead fingers.
In accordance with another aspect of the present invention, a method of forming a semiconductor device package is provided. The method includes providing a lead frame having a die paddle and a plurality of lead fingers. The active surface of a first semiconductor die is then adhered to the underside of the die paddle. At least one of a plurality of bond pads formed on the active surface of the first semiconductor die is electrically connected with a first lead finger of the plurality of lead fingers.
In accordance with yet other aspects of the present invention, a memory device and a computing system are provided. The memory device and computing system each include at least one semiconductor device package configured as set forth herein.